1. Field of the Invention
The present invention relates to an automatic gain control loop, and more particularly, to an automatic gain control loop with a feedback loop.
2. Background of the Related Art
Presently, for radio frequency (RF) receivers, one of two different types of RF architectures, super-heterodyne and direct conversion are used for RF implementation. Generally direct conversion is considered to have the more straight forward approach. Unlike a super heterodyne receiver, a direct conversion receiver directly demodulates a desired signal to a base band signal, and does not need image filtering and Intermediate Frequency Surface Acoustic Wave (IF SAW) filtering. A low pass filter is typically used for channel selection, and thus the direct conversion receiver can be fully integrated. However, despite these architectural advantages, several practical problems, such as channel selection quality and direct current (DC) offsets have limited the availability of direct conversion receivers as commercial products.
FIG. 1 is a general block diagram of a direct conversion receiver 1. An incoming analog RF signal is amplified at a first amplifier stage by a low noise amplifier (LNA) 10. After this front-end amplification, the RF signal is demodulated into the base band signal by a mixer 20 that combines the RF signal with a local oscillation (LO) signal. The demodulated base band signal may be amplified by a post-mixer amplifier 30 and filtered by a channel selection filter 40, for eliminating out-of-band signals. The filtered base band signal is amplified by a second post filter amplifier 50, and is converted to a digital data stream by an analog-to-digital converter (ADC) 60.
Gain assignment and linearity are very important design factors for the direct conversion receiver 1, because channel selection is generally provided at a latter phase of the signal processing. Therefore, amplifiers, here shown as a post-mixer amplifier 30 and post-filter amplifier 50, are generally added to maximize the signal-to-noise ratio (SNR) and dynamic range before and after the channel selection filter 40.
An incoming RF has a time-varying magnitude in its amplitude, and needs gain control to maximize its dynamic range. This gain control should be provided prior to the channel selection filter 40. As shown in FIG. 1, the gain control is provided at the first amplifying stage by replacing the low noise amplifier LNA 10 with an automatic gain controller (AGC). However, since the input signal strength of an AGC can be very small, an input signal having a large input offset and path mismatch can corrupt the desired signal, and saturate the down steam stages.
For example, signal feedthrough leaks can occur at the low noise amplifier 10 input port and at the mixer 20 input port for the local oscillation signal, possibly from capacitor and substrate coupling. This feedthrough (or LO leakage), is mixed with the LO signal, and produces DC offsets. A similar effect occurs when interference leaks from the inputs of the low noise amplifier 10 or the mixer 20, and is multiplied by itself. Further, low frequency device noises, such as 1/f noise and transistor mismatches, contributes to DC offsets. The amount of the produced DC offset voltage can be greater than the input RF signal by more than several tens of dB. If this offset voltage is amplified by down stream gain stages, the amplified offset voltage can saturate the down stream circuits, prohibiting the amplification of the desired signal.
Accordingly, the related art direct conversion receiver 1 requires DC offset cancellation. The related art approach for DC offset cancellation uses a high-pass filtering of the DC offset voltage incorporated within the gain stages. The integration of the high-pass filtering depends on the corner frequency and the amount of DC offset rejection. Since the spectrum of DC offset is restricted around zero frequency, and the high-pass filtering must not impair the desired signal, the desired corner frequency should be as low as possible.
FIGS. 2a–2b show a related art DC offset cancelling circuit 100, having a single feedback loop 120, for providing high pass filtering of a DC offset. The DC offset cancelling circuit 100 includes a plurality of variable gain amplifiers (VGAs) 110 connected in series, and a DC offset cancelling loop 120 connected to an input port of the first VGA 110 and an output port of the last VGA 110. The DC offset cancelling loop 120 includes a DC offset cancelling circuit 130, which is a high pass filter. In FIGS. 2a and 2b, the incoming signal having a voltage Vin is amplified by the variable gain amplifiers (VGA #1, . . . , VGA #N) to the level of an open-loop forward gain Av, and is subjected to a gain of the DC offset cancelling loop Av,DC, a DC offset gain Gm, and a capacitance C of the capacitor 180.
An overall transfer function is shown at Equation 1 as:
                                          V            o                                V            in                          =                              sA            v                                s            +                                                            g                  m                                ⁢                                  A                  v                                ⁢                                  A                                      v                    ,                    DC                                                              C                                                          (        1        )            
The AGC loop 100 has a corner frequency fc shown at Equation 2 as:
                              f          c                =                                            g              m                        ⁢                          A              v                        ⁢                          A                              v                ,                DC                                                          2            ⁢            π            ⁢                                                  ⁢            C                                              (        2        )            
The capacitance C of the DC offset cancelling loop 120 increases as the corner frequency fc decreases and the open loop forward gain Av increases. The capacitance C value typically reaches several hundred of nF, and it is difficult to integrate a capacitor of this value on a single chip. Thus, the capacitor C is typically located at the outside of the chip. Unfortunately, when the off-chip capacitor is wired to the chip, a feedback connection is established, and some amount of noise is added via the bond wire coupling. This noise corrupts the signal integrity and degrades the signal-to-noise ratio (SNR).
For example, according to the above equation 1, the DC offset is reduced at a slope of 20 dB/decade from the corner frequency fc. Rather than suppressing noise, this attenuation of DC offsets often amplifies noise at low frequency. For example, when the corner frequency fc is 100 KHz and the open loop forward gain Av is 80 dB, the offset signal at 100 Hz is amplified by 20 bB. Moreover, lowering the corner frequency fc provides the undesirable effect of reducing the amount of DC offset rejection. Accordingly, related art AGC loops do not simultaneously provide low corner frequency with a high amount of DC offset rejection.